The present invention pertains generally to integrated circuits, and more particularly to a method and apparatus for accelerating the transmission of signals over die interconnects in an integrated circuit via voltage clamping.
The semiconductor industry continues to yield integrated circuits (ICs) of increasing density in order to reduce their overall required chip space and to increase the amount of functionality on a chip. At the same time, logic circuits continue to increase in speed via incremental improvements in component switching times. Even as the performance of electrical components in ICs are improved, however, the maximum achievable speed of the overall circuit still does not approach the achievable level of switching speed of its individual components due to the intrinsic delay, known as RC delay, characteristic of interconnect wires within the die. The resistance of the wire impedes the flow of charge, while the natural capacitance of the wire operates to store charge and therefore impede both the charge and discharge of the wire. Thus, the rate of change in the voltage along a wire when charging the wire to a logical high voltage level is limited by the resistance and capacitance of the wire, resulting in a delay between the time a logical high signal is driven onto the interconnect wire at the driven end of the interconnect wire and the time a receiving component receives the logical high signal at the receiving end of the interconnect wire. Likewise, the rate of change in the voltage along a wire when discharging the wire to a logical low voltage level is limited by the resistance and capacitance of the wire, thus also resulting in a delay between the time a logical low signal is driven onto the interconnect wire at the driven end of the interconnect wire and the time a receiving component receives the logical low signal at the receiving end of the interconnect wire.
Methods have been developed to accelerate the transmission of signals over interconnect wires. One method includes the use of repeater sensors. Repeater sensors are implemented and spaced along the interconnect wire such that each sensor senses and retransmits the signal at full strength to the next sensor across a shorter length of wire. This allows a signal to be retransmitted to the next sensor at full strength before the previous portion of wire has been fully charged. Thus, even though each individual portion of wire between sensors is identically subject to the same resistance and capacitance characteristics as the contiguous wire, the overall RC delay from the driver to the receiver sensor is reduced.
Another method for accelerating signal transmission across interconnect wires is via an interconnect wire tapering technique. With this technique, the interconnect wire is tapered such that it is wider at the driven end and narrower at the receiving end. The presence of a wider wire near the driven end results in less resistance to impede the flow of charge from the driven end towards the receiving end of the wire. However, wider wires have more capacitance. Fortunately, a wider wire near the driven end of the interconnect is less affected by the greater capacitance since the driver is in close proximity to the driven end. Accordingly, if the wire is tapered from wide at the driven end to narrow at the receiving end, the wire benefits from lower resistance on the driven portion of the wire and from lower capacitance at the receiving end. Consequently, a properly tapered interconnect is faster than a constant-width wire.
The techniques described above may not be practically implemented in many ICs. Interconnects are typically run in parallel with other interconnects; accordingly, the space required to implement repeater sensors along intervals of individual interconnects may not be available. Likewise, due to the added complexity of routing a tapered wire, the interconnect wire tapering technique requires more complex and therefore costly routing software and circuit simulation software.
Accordingly, a need exists for a simplified method for accelerating the transmission of signals across interconnect wires.
The present invention is a novel method and apparatus for improving the transmission speed of signals along interconnect wires of an integrated circuit. According to the technique of the invention, a minimum charge level is maintained on the wire when it is driven to a low voltage level and a maximum charge level is maintained on the wire when it is driven to a high voltage level. In accordance with one embodiment of the invention, the minimum and maximum charge levels are maintained on the wire using a pair of clamping circuits which limit the voltage level at the receiving end of the wire to a respective minimum voltage level and maximum voltage level, affecting the charge level on the entire wire to varying degrees. Accordingly, when the interconnect wire is driven to a high voltage level at a driven end of the wire, the charge level on the receiving end of the wire is already at a minimum level (higher than a conventional circuit), resulting in less delay time to charge the wire to a high voltage level. Conversely, when the interconnect wire is driven to a low voltage level at the driven end of the wire, the charge level on the receiving end of the wire is already capped to a maximum level (lower than a conventional circuit), which results in less delay time to drain the wire to a low voltage level.
In one embodiment, the clamping circuits are implemented using diodes. In another embodiment, the clamping circuits are implemented using diode-connected FETs.
The technique of the invention may be combined with other signal transmission accelerating techniques, such as wire tapering and signal repeating, to achieve even higher performance.